1. Field of the Invention
The present invention relates to a method of testing memory with continuous, varying data, wherein test data is continuously input and output through the input and output (I/O) pins of a memory to be tested. Such test data maintains at least a 75% data variation ratio to ensure high accuracy in screening out weakened memory components.
2. Description of Related Art
Memory is a key component in a computer as well as a key element affecting the operational stability of a computer system. As the capacity and speed of memory continue to increase, the manufacturing technology for memory chips has advanced to 0.2 microns or less; the operating voltage lowered to 3.3 volt or less; and the operating speed increased to over 133 MHz. Under such critical operating conditions, a memory chip could be easily weakened or damaged for reasons such as manufacturing errors, outside interference or internal noise. These factors will affect the stability of machine operation. For test engineers, how to sort out weakened memory in a relatively short time has become a challenging task.
With reference to FIGS. 8 and 9, a CMOS inverter is formed with a single-level inverter (11) and a single-level buffer (13). The inputs and outputs of the CMOS inverter are drain voltage (VDD), source voltage (VSS), input voltage (INPUT) and output voltage (OUTPUT). any noise on the drain voltage (VDD) or source voltage (VSS) can cause an error in the output from the inverter. These abnormal outputs could easily cause damage or weaken a memory chip.
Current methods of testing memory include using sophisticated test programs, in which the control pins, address pins and I/O pins of a tested memory chip are preset with a specific values, and complicated data I/O is passed through the tested memory. The test program is then able to determine whether a tested memory has been weakened.
Some of the commonly used memory testing methods are discussed below. With reference to FIG. 10, a conventional memory testing method for activating a single-bank memory sequentially output control signals such as bank active, memory read/write and precharge are to the memory together with a system clock pulse.
With reference to FIGS. 11 and 12, a control I/O operation may activate multiple memory banks. With reference to FIG. 11, the control I/O operation may activate two memory banks (Bank#0 and Bank#1). Furthermore, besides, With reference to FIG. 12, the control I/O operation for activating multiple memory banks can operate on the data I/O for an interleaved memory architecture. Theoretically speaking, when more memory banks are activated, as compared with the memory testing method described in FIG. 10, the accuracy should be higher in detecting weakened memory. However, the detection rate with this method was still rather low.
In order to overcome the drawbacks mentioned above, the present invention provides a method of testing memory with continuous, varying data.